This disclosure relates to integrated circuits and, in particular, integrated circuits with internal pads.
Integrated circuits have increasing numbers of pads. For example, for 72 bit double data rate (DDR) memory devices, each channel may need over 300 I/O pads. The pads may be placed on a perimeter of a substrate. The number and location of such pads create design challenges related to the physical size, signal integrity, power routing, and package design.